u ANALOG
DEVICES
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Quad Precision, High
Speed Operational Amplifier
OP467
Rev. *
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©3–20 Analog Devices, Inc. All rights reserved.
FEATURES
High slew rate: 170 V/μs
Wide bandwidth: 28 MHz
Fast settling time: <200 ns to 0.01%
Low offset voltage: <500 μV
Unity-gain stable
Low voltage operation: ±5 V to ±15 V
Low supply current: <10 mA
Drives capacitive loads
APPLICATIONS
High speed image display drivers
High frequency active filters
Fast instrumentation amplifiers
High speed detectors
Integrators
Photo diode preamps
GENERAL DESCRIPTION
The OP467 is a quad, high speed, precision operational
amplifier. It offers the performance of a high speed op amp
combined with the advantages of a precision op amp in a single
package. The OP467 is an ideal choice for applications where,
traditionally, more than one op amp was used to achieve this
level of speed and precision.
The internal compensation of the OP467 ensures stable unity-
gain operation, and it can drive large capacitive loads without
oscillation. With a gain bandwidth product of 28 MHz driving a
30 pF load, output slew rate is 170 V/μs, and settling time to
0.01% in less than 200 ns, the OP467 provides excellent
dynamic accuracy in high speed data acquisition systems. The
channel-to-channel separation is typically 60 dB at 10 MHz.
The dc performance of the OP467 includes less than 0.5 mV of
offset, a voltage noise density below 6 nV/√Hz, and a total
supply current under 10 mA. The common-mode rejection
ratio (CMRR) is typically 85 dB. The power supply rejection
ratio (PSRR) is typically 107 dB. PSRR is maintained to better than
40 dB with input frequencies as high as 1 MHz. The low offset and
drift plus high speed and low noise make the OP467 usable in
applications such as high speed detectors and instrumentation.
The OP467 is specified for operation from ±5 V to ±15 V over
the extended industrial temperature range (−40°C to +85°C)
and is available in a 14-lead PDIP, a 14-lead CERDIP, a 16-lead
SOIC, and a 20-terminal LCC.
Contact your local sales office for the MIL-STD-883 data sheet
and availability.
PIN CONFIGURATIONS
OUT A
1
–IN A
2
+IN A
3
V+
4
OUT D
14
–IN D
+IN D
V–
+IN C
–IN C
OUT C
13
12
11
+IN B
510
–IN B
6 9
OUT B
7 8
OP467
00302-001
+
+
+
+
Figure 1. 14-Lead CERDIP (Y Suffix) and 14-Lead PDIP (P Suffix)
00302-002
OUT A
–IN A
+IN A
V+
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
NC
+IN B
–IN B
OUT B
NC
OP467
1
2
3
4
16
15
14
13
512
611
710
8 9
NC = NO CONNECT
00302-003
1920123
+IN D
V–
+IN C
NC
NC
OP467
4
5
6
7
8
18
17
16
15
14
131211109
(TOP VIEW)
NC = NO CONNECT
OUT A
OUT D
–IN A
–IN D
+IN A
V+
+IN B
NC
NC
NC
OUT B
OUT C
–IN B
–IN C
NC
Figure 2. 16-Lead SOIC (S Suffix) Figure 3. 20-Terminal LCC (RC Suffix)
00302-004
–IN +IN
V+
V–
OUT
Figure 4. Simplified Schematic
OP467
Rev. I | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Wafer Test Limits .......................................................................... 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
Dice Characteristics ..................................................................... 6
ESD Caution .................................................................................. 6
Typical Performance Characteristics ............................................. 7
Applications Information .............................................................. 13
Output Short-Circuit Performance .......................................... 13
Unused Amplifiers ..................................................................... 13
PCB Layout Considerations ...................................................... 13
Grounding ................................................................................... 13
Power Supply Considerations ................................................... 13
Signal Considerations ................................................................ 13
Phase Reversal ............................................................................ 14
Saturation Recovery Time ......................................................... 14
High Speed Instrumentation Amplifier .................................. 14
2 MHz Biquad Band-Pass Filter ............................................... 15
Fast I-to-V Converter ................................................................ 16
OP467 SPICE Marco-Model ..................................................... 17
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
4/10—Rev. H to Rev. I
Deleted Endnote 2 From Table 1 .................................................... 3
8/09—Rev. G to Rev. H
Changes to Table 4 ............................................................................ 6
4/09—Rev. F to Rev. G
Changes to Power Supply Considerations Section ..................... 13
5/07—Rev. E to Rev. F
Updated Format .................................................................. Universal
Changes to General Description .................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
3/04—Rev. D to Rev. E
Changes to TPC 1 .............................................................................. 5
Changes to Ordering Guide ............................................................. 4
Updated Outline Dimensions ....................................................... 16
4/01—Rev. C to Rev. D
Footnote added to Power Supply ..................................................... 2
Footnote added to Max Ratings ...................................................... 4
Edits to Power Supply Considerations Section ........................... 11
OP467
Rev. I | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ VS = ±15.0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 0.2 0.5 mV
−40°C ≤ TA ≤ +85°C 1 mV
Input Bias Current IB VCM = 0 V 150 600 nA
V
CM = 0 V, −40°C ≤ TA ≤ +85°C 150 700 nA
Input Offset Current IOS VCM = 0 V 10 100 nA
V
CM = 0 V, −40°C ≤ TA ≤ +85°C 10 150 nA
Common-Mode Rejection CMR VCM = ±12 V 80 90 dB
CMR VCM = ±12 V, −40°C ≤ TA ≤ +85°C 80 88 dB
Large Signal Voltage Gain AVO RL = 2 kΩ 83 86 dB
R
L = 2 kΩ, −40°C ≤ TA ≤ +85°C 77.5 dB
Offset Voltage Drift ΔVOS/ΔT 3.5 μV/°C
Bias Current Drift ΔIB/ΔT 0.2 pA/°C
Long-Term Offset Voltage Drift1 ΔVOS/ΔT 750 μV
OUTPUT CHARACTERISTICS
Output Voltage Swing VO RL = 2 kΩ ±13.0 ±13.5 V
R
L = 2 kΩ, −40°C ≤ TA ≤ +85°C ±12.9 ±13.12 V
POWER SUPPLY
Power Supply Rejection Ratio PSRR ±4.5 V ≤ VS ≤ ±18 V 96 120 dB
−40°C ≤ TA ≤ +85°C 86 115 dB
Supply Current ISY VO = 0 V 8 10 mA
V
O = 0 V, −40°C ≤ TA ≤ +85°C 13 mA
Supply Voltage Range VS ±4.5 ±18 V
DYNAMIC PERFORMANCE
Gain Bandwidth Product GBP AV = +1, CL = 30 pF 28 MHz
Slew Rate SR VIN = 10 V step, RL = 2 kΩ, CL = 30 pF
A
V = +1 125 170 V/μs
A
V = −1 350 V/μs
Full-Power Bandwidth BWρ VIN = 10 V step 2.7 MHz
Settling Time tS To 0.01%, VIN = 10 V step 200 ns
Phase Margin θ0 45 Degrees
Input Capacitance
Common Mode 2.0 pF
Differential 1.0 pF
NOISE PERFORMANCE
Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 0.15 μV p-p
Voltage Noise Density eN f = 1 kHz 6 nV/√Hz
Current Noise Density iN f = 1 kHz 0.8 pA/√Hz
1 Long-term offset voltage drift is guaranteed by 1000 hrs. Life test performed on three independent wafer lots at 125°C, with an LTPD of 1.3.
OP467
Rev. * | Page 4 of 20
@ VS = ±5.0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 0.3 0.5 mV
−40°C ≤ TA ≤ +85°C 1 mV
Input Bias Current IB VCM = 0 V 125 600 nA
V
CM = 0 V, −40°C ≤ TA ≤ +85°C 150 700 nA
Input Offset Current IOS VCM = 0 V 20 100 nA
V
CM = 0 V, −40°C ≤ TA ≤ +85°C 150 nA
Common-Mode Rejection CMR VCM = ±2.0 V 76 85 dB
CMR VCM = ±2.0 V, −40°C ≤ TA ≤ +85°C 76 80 dB
Large Signal Voltage Gain AVO RL = 2 kΩ 80 83 dB
R
L = 2 kΩ, −40°C ≤ TA ≤ +85°C 74 dB
Offset Voltage Drift ΔVOS/ΔT 3.5 μV/°C
Bias Current Drift ΔIB/ΔT 0.2 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage Swing VO RL = 2 kΩ ±3.0 ±3.5 V
R
L = 2 kΩ, −40°C ≤ TA ≤ +85°C ±3.0 ±3.20 V
POWER SUPPLY
Power Supply Rejection Ratio PSRR ±4.5 V ≤ VS ≤ ±5.5 V 92 107 dB
−40°C ≤ TA ≤ +85°C 83 105 dB
Supply Current ISY VO = 0 V 8 10 mA
V
O = 0 V, −40°C ≤ TA ≤ +85°C 12 mA
DYNAMIC PERFORMANCE
Gain Bandwidth Product GBP AV = +1 22 MHz
Slew Rate SR VIN = 5 V step, RL = 2 kΩ, CL = 39 pF
A
V = +1 90 V/μs
A
V = −1 90 V/μs
Full-Power Bandwidth BWρ VIN = 5 V step 2.5 MHz
Settling Time tS To 0.01%, VIN = 5 V step 280 ns
Phase Margin θ0 45 Degrees
NOISE PERFORMANCE
Voltage Noise eN p-p f = 0.1 Hz to 10 Hz 0.15 μV p-p
Voltage Noise Density eN f = 1 kHz 7 nV/√Hz
Current Noise Density iN f = 1 kHz 0.8 pA/√Hz
OP467
Rev. * | Page 5 of 20
WAFER TEST LIMITS1
@ VS = ±15.0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Limit Unit
Offset Voltage VOS ±0.5 mV max
Input Bias Current IB VCM = 0 V 600 nA max
Input Offset Current IOS VCM = 0 V 100 nA max
Input Voltage Range2 ±12 V min/max
Common-Mode Rejection Ratio CMRR VCM = ±12 V 80 dB min
Power Supply Rejection Ratio PSRR V = ±4.5 V to ±18 V 96 dB min
Large Signal Voltage Gain AVO RL = 2 kΩ 83 dB min
Output Voltage Range VO RL = 2 kΩ ±13.0 V min
Supply Current ISY VO = 0 V, RL = ∞ 10 mA max
1 Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult sales to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
2 Guaranteed by CMR test.
ESD (elemosmic discharge) sensikive deviu,
Chavged devlces and mum boavds can dwschavge
wnhoul daemon Akhough mu pmduu lemme;
paxemed 0v pmpuemy pvmemon (Ivcumy, damage
may cum on dewzei Sumeded m hwgh enevgy ESD
Theyeiove, pmpev ESD pvezaunons mama be (aken m
avold pevvovmance degradanon av loss of fundlonamy
OP467
Rev. * | Page 6 o
f 20
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter1Rating
Supply Voltage ±18 V
Input Voltage2
±18 V
Differential Input Voltage2
±26 V
Output Short-Circuit Duration Limited
Storage Temperature Range
14-Lead CERDIP and 20-Terminal LCC −65°C to +175°C
14-Lead PDIP and 16-Lead SOIC −65°C to +150°C
Operating Temperature Range
OP467A −55°C to +125°C
OP467G −40°C to +85°C
Junction Temperature Range
14-Lead CERDIP and 20-Terminal LCC −65°C to +175°C
14-Lead PDIP and 16-Lead SOIC −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
1 Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2 For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5.
Package Type θJA1 θ
JC Unit
14-Lead CERDIP (Y) 94 10 °C/W
14-Lead PDIP (P) 76 33 °C/W
16-Lead SOIC (S) 88 23 °C/W
20-Terminal LCC (RC) 78 33 °C/W
1 θJA is specified for the worst-case conditions, that is, θJA is specified for device
in socket for CERDIP, PDIP, and LCC packages, and θJA is specified for device
soldered in circuit board for the SOIC package.
DICE CHARACTERISTICS
00302-005
12
3
4
5
6789
10 +IN C
–IN C
+IN D
–IN D
–IN A
+IN A
+IN B
–IN B
V+
OUT D
OUT A
T C
T B
V–
11
12
13
14
OU
OU
Figure 5. 0.111 Inch × 0.100 Inch DIE Size, 11,100 sq. mils,
Substrate Connected to V+, 165 Transistors
ESD CAUTION
AVCL:¢1D
\\
OP467
Rev. * | Page 7 of 20
–20
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
00
TYPICAL PERFORMANCE CHARACTERISTICS
20
30
40
50
60
70
80
–10
–90
–135
–180
0
10
OPEN-LOOP GAIN (dB)
PHASE SHIFT (Degrees)
302-006
V
S
= ±15V
R
L
= 1MΩ
C
L
= 30pF
GAIN
PHASE
Figure 6. Open-Loop Gain, Phase vs. Frequency
40
60
80
–20
0
20
CLOSED-LOOP GAIN (dB)
00302-007
10k 100k 1M 10M 100M
FREQUENCY (Hz)
V
S
= ±15V
T
A
= 25°C
Figure 7. Closed-Loop Gain vs. Frequency
00302-008
25
10
0
5
15
20
OPEN-LOOP GAIN (V/mV)
T
A
= +25°C
0±5 ±10 ±15 ±20
SUPPLY VOLTAGE (V)
T
A
= +125°C
T
A
= –55°C
Figure 8. Open-Loop Gain vs. Supply Voltage
60
80
100
20
0
40
100 1k 10k 100k 1M
IMPEDANCE (Ω)
FREQUENCY (Hz)
00302-009
V
S
= ±15V
T
A
= 25°C
A
VCL
= +100
A
VCL
= +10
A
VCL
= +1
Figure 9. Closed-Loop Output Impedance vs. Frequency
–0.3
3.4 5.8
–0.2
–0.1
0.0
0.1
0.2
0.3
0
100k 1M 10M
GAIN ERROR (dB)
FREQUENCY (Hz)
00302-010
V
S
= ±5V
V
S
= ±15V
Figure 10. Gain Error vs. Frequency
15
20
25
30
0
5
10
1k 10k 100k 1M 10M
MAXIMUM OUTPUT SWING (V)
FREQUENCY (Hz)
00302-011
A
VCL
= +1
A
VCL
= –1
V
S
= ±15V
T
A
= 25°C
R
L
= 2kΩ
Figure 11. Maximum VOUT Swing vs. Frequency
Am = ‘1 /
g\\
OP467
Rev. * | Page 8 of 20
0
2
1k 10k 100k 1M 10M
00302-012
6
8
10
12
4
MAXIMUM OUTPUT SWING (V)
FREQUENCY (Hz)
A
VCL
= –1
A
VCL
= +1
V
S
= ±5V
T
A
= 25°C
R
L
= 2kΩ
Figure 12. Maximum VOUT Swing vs. Frequency
60
80
100
120
20
40
COMMON-MODE REJECTION (V)
0
1k 10k 100k 1M 10M
00302-013
FREQUENCY (Hz)
V
S
= ±15V
T
A
= 25°C
Figure 13. Common-Mode Rejection vs. Frequency
60
80
100
120
20
40
POWER SUPPLY REJECTION (dB)
0
100 1k 10k 100k 1M
FREQUENCY (Hz)
00302-014
V
S
= ±15V
T
A
= 25°C
Figure 14. Power-Supply Rejection vs. Frequency
30
40
50
60
0
10
20
0200 400 600
OVERSHOOT (%)
LOAD CAPACITANCE (pF)
00302-015
800 1000 1200 1400 1600
V
S
= ±15V
R
L
= 2kΩ
V
VIN
= 100mV p-p
A
VCL
= +1
A
VCL
= –1
Figure 15. Small Signal Overshoot vs. Load Capacitance
30
40
50
60
0
10
20
0200 400 600
OVERSHOOT (%)
LOAD CAPACITANCE (pF)
00302-016
800 1000 1200 1400 1600
V
S
= ±15V
R
L
= 2kΩ
V
VIN
= 100mV p-p
A
VCL
= +1
A
VCL
= –1
Figure 16. Small Signal Overshoot vs. Load Capacitance
10
20
30
40
50
60
–40
–30
–20
–10
0
10k 100k 1M
GAIN (dB)
FREQUENCY (Hz)
00302-017
10M 100M
V
S
= ±15V
10000pF
1000pF 500pF
200pF
C
IN
= NETWORK
ANALYZER
Figure 17. Noninverting Gain vs. Capacitive Loads
E, E
OP467
Rev. * | Page 9 of 20
–100
–90
100 1k 10k 100k
00302-018
1M 10M 100M
–50
–40
–30
–20
–10
0
–80
–70
–60
CHANNEL SEPARATION (dB)
FREQUENCY (Hz)
V
S
= ±15V
0
110 100
INP
00302-019
1k
Figure 18. Channel Separation vs. Frequency
10
12
2
4
6
8
UT CURRENT NOISE DENSITY (pA/√Hz)
FREQUENCY (Hz)
±5V ≤ V
S
≤ 15V
Figure 19. Input Current Noise Density vs. Frequency
10
100
TAGE NOISE DENSITY (nV/√Hz)
1.0
0.1 1 10 100 1k 10k
VOL
FREQUENCY (Hz)
00302-020
Figure 20. Voltage Noise Density vs. Frequency
0
1
2
3
4
–4
–3
–2
–1
0100 200 300 400 500
V
OUT
ERROR (mV)
TIME (ns)
00302-021
V
S
= ±15V
V
IN
= ±5V
C
L
= 50pF
Figure 21. Settling Time, Negative Edge
0
1
2
3
4
–4
–3
–2
–1
0100 200 300 400 500
V
OUT
ERROR (mV)
TIME (ns)
00302-022
V
S
= ±15V
V
IN
= ±5V
C
L
= 50pF
Figure 22. Settling Time, Positive Edge
0
5
10
15
20
–20
–15
–10
–5
0±5 ±10 ±15 ±20
INPUT VOLTAGE RANGE (V)
SUPPLY VOLTAGE (V)
00302-023
T
A
= 25°C
Figure 23. Input Voltage Range vs. Supply Voltage
OP467
Rev. * | Page 10 of 20
00302-024
10k 100k 1M 10M 100M
GAIN (dB)
–10
10
20
30
40
0
50
FREQUENCY (Hz)
V
S1
= ±15V
–50
–40
–30
–20
V
S2
= ±5V
V
S1
= ±15V
V
S2
= ±5V
R
L
= 10kΩ
C
L
= 50pF
Figure 24. Noninverting Gain vs. Supply Voltage
10
12
14
4
6
8
OUTPUT SWING (V)
0
2
10 100 1k
00302-025
10k
LOAD RESISTANCE (Ω)
V
S
= ±15V
T
A
= 25°C
POSITIVE
SWING
NEGATIVE
SWING
Figure 25. Output Swing vs. Load Resistance
4
5
1
2
3
OUTPUT SWING (V)
0
10 100 1k
LOAD RESISTANCE (Ω)
00302-026
10k
NEGATIVE
SWING
POSITIVE
SWING
VS = ±15V
TA = 25°C
Figure 26. Output Swing vs. Load Resistance
UNITS
INPUT OFFSET VOLTAGE (V
OS
µV)
00302-027
500
0
100
200
300
400
–100 –50 0 50 100 150 200 250 300 350 400
V
S
= ±15V
T
A
= 25°C
1252 × OP AMPS
Figure 27. Input Offset Voltage Distribution
UNITS
INPUT OFFSET VOLTAGE (V
OS
µV)
00302-028
500
0
100
200
300
400
–100 –50 0 50 100 150 200 250 300 350 400
V
S
= ±5V
T
A
= 25°C
1252 × OP AMPS
Figure 28. Input Offset Voltage Distribution
UNITS
TC V
OS
(µV/°C)
00302-029
500
0
100
200
300
400
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
S
= ±15V
T
A
= 25°C
1252 × OP AMPS
Figure 29. TC VOS Distribution
OP467
Rev. * | Page 11 of 20
UNITS
TC V
OS
(µV/°C)
00302-030
500
0
100
200
300
400
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
S
= ±5V
T
A
= 25°C
1252 × OP AMPS
GA
00302-031
40 27.0
–75 –50 –25 0 25 50 75 100 125
Figure 30. TC VOS Distribution
PHASE MARGIN (Degrees)
IN BANDWIDTH PRODUCT (MHz)
60
45
50
55
29.0
27.5
28.0
28.5
TEMPERATURE (°C)
GBW
ФM
V
S
= ±5V
R
L
= 2kΩ
Figure 31. Phase Margin and Gain Bandwidth vs. Temperature
SLEW RATE (V/µs )
400
50
100
150
200
250
300
350
–SR
+SR
TEMPERATURE (°C)
00302-032
0
–75 –50 –25 0 25 50 75 100 125
V
S
= ±5V
R
L
= 2kΩ
A
VCL
=–1
Figure 32. Slew Rate vs. Temperature
SLEW RATE (V/µs)
TEMPERATURE (°C)
00302-033
400
0
50
100
150
200
250
300
350
–75 –50 –25 0 25 50 75 100 125
–SR
+SR
V
S
= ±5V
R
L
= 2kΩ
A
VCL
=+1
Figure 33. Slew Rate vs. Temperature
SLEW RATE (V/µs)
TEMPERATURE (°C)
00302-034
650
250
300
350
400
450
500
550
600
–75 –50 –25 0 25 50 75 100 125
–SR
+SR
V
S
= ±15V
R
L
= 2kΩ
A
VCL
=–1
Figure 34. Slew Rate vs. Temperature
SLEW RATE (V/µs)
TEMPERATURE (°C)
00302-035
400
0
50
100
150
200
250
300
350
–75 –50 –25 0 25 50 75 100 125
–SR
+SR
V
S
= ±15V
R
L
= 2kΩ
A
VCL
=+1
Figure 35. Slew Rate vs. Temperature
OP467
UTPUT STEP FOR ±15V SUPPLY (V)
10
–6
–4
–2
0
2
4
6
8
0.1%
0.1%
0.1%
Rev. * | Page 12 of 20
O
00302-036
–10
–8
0 100 200 300 400
0.1%
SETTLING TIME (ns)
O
–1
–2
UTPUT STEP FOR ±5V SUPPLY (V)
–3
–4
–5
0
1
2
3
4
5
R
F
= 5kΩ
T
A
=25°C
Figure 36. Output Step vs. Settling Time
SUPPLY CURRENT (mA)
10
4
6
8
SUPPLY VOLTAGE (V)
00302-037
0
2
0 ±5 ±10 ±15 ±20
T
A
= +125°C
T
A
= +25°C
T
A
= –55°C
Figure 37. Supply Current vs. Supply Voltage
INPUT BIAS CURRENT (nA)
TEMPERATURE (°C)
00302-038
200
0
40
90
120
160
–75 –50 –25 0 25 50 75 100 125
V
S
=±15V
Figure 38. Input Bias Current vs. Temperature
INPUT OFFSET CURRENT (nA)
TEMPERATURE (°C)
00302-039
25
0
5
10
15
20
–75 –50 –25 0 25 50 75 100 125
V
S
=±15V
Figure 39. Input Offset Current vs. Temperature
OP467
Rev. * | Page 13 of 20
APPLICATIONS INFORMATION
OUTPUT SHORT-CIRCUIT PERFORMANCE
To achieve a wide bandwidth and high slew rate, the OP467
output is not short-circuit protected. Shorting the output to
ground or to the supplies may destroy the device.
For safe operation, the output load current should be limited so
that the junction temperature does not exceed the absolute
maximum junction temperature.
The maximum internal power dissipation can be calculated by
JA
D
Pθ
=A
JTT −max
where:
TJ and TA are junction and ambient temperatures, respectively.
PD is device internal power dissipation.
θJA is the packaged device thermal resistance given in the data sheet.
UNUSED AMPLIFIERS
It is recommended that any unused amplifiers in the quad
package be connected as a unity-gain follower with a 1 kΩ
feedback resistor with noninverting input tied to the ground plain.
PCB LAYOUT CONSIDERATIONS
Satisfactory performance of a high speed op amp largely
depends on a good PCB layout. To achieve the best dynamic
performance, follow the high frequency layout technique.
GROUNDING
A good ground plain is essential to achieve the optimum
performance in high speed applications. It can significantly
reduce the undesirable effects of ground loops and IR drops by
providing a low impedance reference point. Best results are
obtained with a multilayer board design with one layer assigned
to the ground plain. To maintain a continuous and low impedance
ground, avoid running any traces on this layer.
POWER SUPPLY CONSIDERATIONS
In high frequency circuits, device lead length introduces an
inductance in series with the circuit. This inductance, combined
with stray capacitance, forms a high frequency resonance circuit.
Poles generated by these circuits cause gain peaking and additional
phase shift, reducing the phase margin of the op amp and leading
to an unstable operation.
A practical solution to this problem is to reduce the resonance
frequency low enough to take advantage of the power supply
rejection of the amplifier. This is easily done by placing capacitors
across the supply line and the ground plane as close as possible
to the device pin. Because capacitors also have internal parasitic
components, such as stray inductance, selecting the right capacitor
is important. To be effective, they should have low impedance
over the frequency range of interest. Tantalum capacitors are an
excellent choice for their high capacitance/size ratio, but their
effective series resistance (ESR) increases with frequency
making them less effective.
On the other hand, ceramic chip capacitors have excellent ESR
and effective series inductance (ESL) performance at higher
frequencies, and because of their small size, they can be placed
very close to the device pin, further reducing the stray inductance.
Best results are achieved by using a combination of these two
capacitors. A 5 F to 10 F tantalum parallel capacitor with a
0.1 F ceramic chip capacitor is recommended. If additional
isolation from high frequency resonances of the power supply is
needed, a ferrite bead should be placed in series with the supply
lines between the bypass capacitors and the power supply. Note
that addition of the ferrite bead introduces a new pole and zero
to the frequency response of the circuit and could cause unstable
operation if it is not selected properly.
00302-040
+V
S
+10µF TANTALUM
0.1µF CERAMIC CHIP
–V
S
10µF TANTALUM
0.1µF CERAMIC CHIP
Figure 40. Recommended Power Supply Bypass
SIGNAL CONSIDERATIONS
Input and output traces need special attention to assure a
minimum stray capacitance. Input nodes are very sensitive to
capacitive reactance, particularly when connected to a high
impedance circuit. Stray capacitance can inject undesirable
signals from a noisy line into a high impedance input. Protect
high impedance input traces by providing guard traces around
them, which also improves the channel separation significantly.
Additionally, any stray capacitance in parallel with the input
capacitance of the op amp generates a pole in the frequency
response of the circuit. The additional phase shift caused by this
pole reduces the gain margin of the circuit. If this pole is within
the gain range of the op amp, it causes unstable performance. To
reduce these undesirable effects, use the lowest impedance
where possible. Lowering the impedance at this node places the
poles at a higher frequency, far above the gain range of the
amplifier. Stray capacitance on the PCB can be reduced by making
the traces narrow and as short as possible. Further reduction
can be realized by choosing a smaller pad size, increasing the
spacing between the traces, and using PCB material with a low
dielectric constant insulator (dielectric constant of some common
insulators: air = 1, Teflon® = 2.2, and FR4 = 4.7, with air being
an ideal insulator).
Removing segments of the ground plane directly under the
input and output pads is recommended.
|
OP467
Rev. * | Page 14 of 20
Outputs of high speed amplifiers are very sensitive to capacitive
loads. A capacitive load introduces a pair of pole and zero to the
frequency response of the circuit, reducing the phase margin,
leading to unstable operation or oscillation.
Generally, it is good design practice to isolate the output of the
amplifier from any capacitive load by placing a resistor between
the output of the amplifier and the rest of the circuits. A series
resistor of 10 to 100 is normally sufficient to isolate the
output from a capacitive load.
The OP467 is internally compensated to provide stable
operation and is capable of driving large capacitive loads
without oscillation.
Sockets are not recommended because they increase the lead
inductance/capacitance and reduce the power dissipation of the
package by increasing the thermal resistance of the leads. If
sockets must be used, use Teflon or pin sockets with the shortest
possible leads.
PHASE REVERSAL
The OP467 is immune to phase reversal; its inputs can exceed
the supply rails by a diode drop without any phase reversal.
00302-041
INTPUT
OUTPUT
15.8VΔV1
200µs10V10V
100
90
10
0%
Figure 41. No Phase Reversal (AV = +1)
SATURATION RECOVERY TIME
The OP467 has a fast and symmetrical recovery time from
either rail. This feature is very useful in applications such as
high speed instrumentation and measurement circuits, where
the amplifier is frequently exposed to large signals that overload
the amplifier.
00302-042
DLY 9.824µs
20ns5V5V
100
90
10
0%
Figure 42. Saturation Recovery Time, Positive Rail
00302-043
DLY 4.806µs
20ns5V5V
100
90
10
0%
Figure 43. Saturation Recovery Time, Negative Rail
HIGH SPEED INSTRUMENTATION AMPLIFIER
The OP467 performance lends itself to a variety of high speed
applications, including high speed precision instrumentation
amplifiers. Figure 44 represents a circuit commonly used for
data acquisition, CCD imaging, and other high speed
applications.
The circuit gain is set by RG. A 2 kΩ resistor sets the circuit gain
to 2; for unity gain, remove RG. For any other gain settings, use
the following formula
G = 2/RG (Resistor Value is in kΩ)
RC is used for adjusting the dc common-mode rejection, and CC
is used for ac common-mode rejection adjustments.
00302-044
+V
IN
–V
IN
1kΩ2kΩ
2kΩ
2kΩOUTPUT
1kΩ
10kΩ
1.9kΩ
200Ω
10T
R
C
5pF
R
G
10kΩ
C
C
Figure 44. A High Speed Instrumentation Amplifier
OP467
Rev. * | Page 15 of 20
00302-045
2 MHz BIQUAD BAND-PASS FILTER
0.01% 10V STEP
V
S
= ±15V
NEG SLOPE
The circuit in Figure 48 is commonly used in medical imaging
ultrasound receivers. The 30 MHz bandwidth is sufficient to
accurately produce the 2 MHz center frequency, as the measured
response shows in Figure 49. When the bandwidth of the op
amp is too close to the center frequency of the filter, the internal
phase shift of the amplifier causes excess phase shift at 2 MHz,
which alters the response of the filter. In fact, if the chosen op
amp has a bandwidth close to 2 MHz, the combined phase shift
of the three op amps causes the loop to oscillate.
2.5mV
–2.5mV
Careful consideration must be given to the layout of this circuit
as with any other high speed circuit.
Figure 45. Instrumentation Amplifier Settling Time to 0.01% for a
10 V Step Input (Negative Slope) If the phase shift introduced by the layout is large enough, it can
alter the circuit performance, or worse, cause oscillation.
00302-046
0.01% 10V STEP
V
S
=±15V
POS SLOPE
2.5mV
–2.5mV
00302-048
V
IN
V
OUT
1/4
OP467
1/4
OP467
1/4
OP467 1/4
OP467
R1
3kΩ
2kΩ
R2
2kΩ
R6
1kΩ
C1
50pF
C2
50pF
R3
2kΩ
R4
2kΩ
R5
2kΩ
Figure 46. Instrumentation Amplifier Settling Time to 0.01% for a
10 V Step Input (Positive Slope) Figure 48. 2 MHz Biquad Filter
00302-047
+V
S
AD9617
GAIN (dB)
FREQUENCY (Hz)
00302-049
–30
–20
–10
0
10k 100k 1M 10M 100M
–40
+
+
–V
S
2kΩ
1kΩ
TO
INPUT
TO
IN-AMP
OUTPUT
ERROR
TO SCOPE
2kΩ
61.9Ω549Ω
Figure 47. Settling Time Measurement Circuit
Figure 49. Biquad Filter Response
L
W
_ . . _
0* . 0P461 oPAs7 . —o
.g j} .
v :I v .
S E %
LILILIULILI
W
4
O
a
mmmmmma#L%
W
V9
i
OP467
Rev. * | Page 16 of 20
00302-050
15
V
DD
V
REF
AV
REF
C
R
FB
AR
FB
C
R
FB
BR
FB
D
V
REF
BV
REF
D
DB0 (LSB) DS2
I
OUT 1A
I
OUT 1C
I
OUT 2A/
I
OUT 2C/
I
OUT 2B
I
OUT 2D
I
OUT 1B
I
OUT 1D
DGND
DAC8408
OUT A
OUT B
OUT D
OUT C
C1
10pF
C3
10pF
C4
10pF
C2
10pF
7
5
4
11
6
OP467
OP467
1
1
2
3
7
8
9
10
11
12
4
5
6
13
14
DIGITAL
CONTROL
SIGNALS
DB1
DB2
DB3
DB4
DB5
(MSB) DB7
DB6
28
27
26
22
21
20
19
18
17
25
24
23
16
R/W
A/B
DS1
0.1µF
0.1µF
+15V
+10V
+10V
+5V
+10V +10V
–15V
2
3
OP467
14
12
13
OP467
8
10
9
Figure 50. Quad DAC Unipolar Operation
FAST I-TO-V CONVERTER
The fast slew rate and fast settling time of the OP467 are well
suited to the fast buffers and I-to-V converters used in a variety
of applications. The circuit in Figure 50 is a unipolar quad DAC
consisting of only two ICs. The current output of the DAC8408
is converted to a voltage by the OP467 configured as an I-to-V
converter. This circuit is capable of settling to 0.1% within 200 ns.
Figure 51 and Figure 52 show the full-scale settling time of the
outputs. To obtain reliable circuit performance, keep the traces
from the IOUT of the DAC to the inverting inputs of the OP467
short to minimize parasitic capacitance.
00302-051
260.0ns
100ns50mV2V
100
90
10
0%
Figure 51. Falling Edge Output Settling Time
00302-052
251.0ns
100ns50mV2V
100
90
10
0%
Figure 52. Rising Edge Output Settling Time
00302-053
2kΩ
2kΩ
1kΩ
60.4kΩ
604Ω
50kΩ
3pF
DAC8408 DC OFFSET
R
FB
I
OUT
I-V
OP467
AD847
Figure 53. DAC VOUT Settling Time Circuit
OP467
Rev. * | Page 17 of 20
OP467 SPICE MARCO-MODEL
* Node assignments
noninverting input
inverting input
positive supply
negative supply
output
*
. SUBCKT OP467 1 2 99 50 27
*
* INPUT STAGE
*
I1 4
5
0
10E–3
CIN 1 2 1E–12
IOS 1 2 5E–9
Q1 5 2 8 QN
Q2 6 7 9 QN
R3 99 5 185 . 681
R4 99 6 185 . 681
R5 8 4 180 . 508
R6 9 4 180 . 508
EOS 7 1 POLY (1) (14,20) 50E–6 1
EREF 98 0 (20,0) 1
*
* GAIN STAGE AND DOMINANT POLE AT 1.5 kHz
*
R7 10 98 3 . 714E6
C2 10 98 28 . 571E–12
G1 98 10 (5,6) 5 . 386E–3
V1 99 11 1 . 6
V2 12 50 1 . 6
D1 10 11 DX
D2 12 10 DX
RC 10 28 1 . 4E3
CC 28 27 12E–12
*
* COMMON-MODE STAGE WITH ZERO AT 1.26 kHz
*
ECM 13 98 POLY (2) (1, 20) (2,20) 0 0. 5 0 . 5
R8 13 14 1E6
R9 14 98 25 . 119
C3 13 14 126 . 721E–12
*
*POLE AT 400E6
*
R10 15 98 1E6
C4 15 98 0 . 398E–15
G2 98 15 (10,20) 1E–6
*
* OUTPUT STAGE
*
ISY 99 50 –8 . 183E–3
RMP1 99 20 96 . 429E3
RMP2 20 50 96 . 429E3
RO1 99 26 200
RO2 26 50 200
L1 26 27 1E–7
GO1 26 99 (99,15) 5E–3
GO2 50 26 (15,50) 5E–3
G4 23 50 (15,26) 5E–3
G5 24 50 (26,15) 5E–3
V3 21 26 50
V4 26 22 50
D3 15 21 DX
D4 22 15 DX
D5 99 23 DX
D6 99 24 DX
D7 50 23 DY
D8 50 24 DY
*
* MODELS USED
*
. MODEL QN NPN (BF=33.333E3)
. MODEL DX D
. MODEL DY D (BV=50)
. ENDS OP467
OP467
G2
R10
C4
I
SY
RMP2
RMP1
20
15
D5
D3
D4
D6
23 24
22
21
V3
V4
G01
R02
R01
L1
99
26
15
99
27
Rev. * | Page 18 of 20
00302-054
E
REF
G4 D7 G5
D8 G02
50 50
–
+
98
–+
–+
Figure 54. SPICE Macro-Model Output Stage
00302-055
I
OS
C
IN
I1
E
OS
R3
5
G1
99 99
N+
2
1
R4
6
R5 R6
4
89
7
C2
R7
10
98
12
E
REF
R
C
E
CM
C
C
28
C3
R8 14
27
V1
11
13
D2
D1
R9
50 50
V2
–
+
Q1 Q2
N–
–
+
–+
–
+
–
+
Figure 55. SPICE Macro-Model Input and Gain Stage
OP467
Rev. I | Page 19 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
070606-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
14
17
8
0.100 (2.54)
BSC
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 56. 14-Lead Plastic Dual In-Line Package [PDIP]
(N-14)
P-Suffix
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.310 (7.87)
0.220 (5.59)
0.005 (0.13) MIN 0.098 (2.49) MAX
0.100 (2.54) BSC
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.785 (19.94) MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
PIN 1
17
8
14
Figure 57. 14-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-14)
Y-Suffix
Dimensions shown in inches and (millimeters)
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OP467
Rev. I | Page 20 of 20
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013- AA
032707-B
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
Figure 58. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
S-Suffix
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
1
20 4
9
8
13
19
14
3
18
BOTTOM
VIEW
0.028 (0.71)
0.022 (0.56)
45° TYP
0.015 (0.38)
MIN
0.055 (1.40)
0.045 (1.14)
0.050 (1.27)
BSC
0.075 (1.91)
REF
0.011 (0.28)
0.007 (0.18)
R TYP
0.095 (2.41)
0.075 (1.90)
0.100 (2.54) REF
0.200 (5.08)
REF
0.150 (3.81)
BSC
0.075 (1.91)
REF
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
022106-A
Figure 59. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1) RC-Suffix
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
OP467GP −40°C to +85°C 14-Lead PDIP N-14
OP467GPZ −40°C to +85°C 14-Lead PDIP N-14
OP467GS −40°C to +85°C 16-Lead SOIC_W RW-16
OP467GS-REEL −40°C to +85°C 16-Lead SOIC_W RW-16
OP467GSZ −40°C to +85°C 16-Lead SOIC_W RW-16
OP467GSZ-REEL −40°C to +85°C 16-Lead SOIC_W RW-16
OP467ARC/883C −55°C to +125°C 20-Terminal LCC E-20-1
OP467AY/883C −55°C to +125°C 14-Lead CERDIP Q-14
OP467GBC Die
1 Z = RoHS Compliant Part.
©1993–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00302-0-4/10(I)
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